Practical Asynchronous Interconnect Network Design

TitlePractical Asynchronous Interconnect Network Design
Publication TypeJournal Article
Year of Publication2008
AuthorsQuinton, B. R., M. R. Greenstreet, and S. J. E. Wilton
JournalVery Large Scale Integration (VLSI) Systems, IEEE Transactions on
Volume16
Pagination579 -588
Date Publishedmay.
ISSN1063-8210
Keywordsasynchronous circuits, asynchronous interconnect network design, IC interconnect, integrated circuit interconnections, network-on-chip
Abstract

The implementation of interconnect is becoming a significant challenge in modern integrated circuit (IC) design. Both synchronous and asynchronous strategies have been suggested to manage this problem. Creating a low skew clock tree for synchronous inter-block pipeline stages is a significant challenge. Asynchronous interconnect does not require a global clock, and therefore, it has a potential advantage in terms of design effort. This paper presents an asynchronous interconnect design that can be implemented using a standard application-specific IC flow. This design is considered across a range of IC interconnect scenarios. The results demonstrate that there is a region of the design space where the implementation provides an advantage over a synchronous interconnect by removing the need for clocked inter-block pipeline stages, while maintaining high throughput. Further results demonstrate a computer-aided design tool enhancement that would significantly increase this space. A detailed comparison of power, area, and latency of the two strategies is also provided for a range of IC scenarios.

URLhttp://dx.doi.org/10.1109/TVLSI.2008.917545
DOI10.1109/TVLSI.2008.917545

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