Concentrator access networks for programmable logic cores on SoCs

TitleConcentrator access networks for programmable logic cores on SoCs
Publication TypeConference Paper
Year of Publication2005
AuthorsQuinton, B. R., and S. J. E. Wilton
Conference NameCircuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Pagination45 - 48 Vol. 1
Date Publishedmay.
Keywordsconcentrator access networks, input/output ordering, programmable logic cores, programmable logic devices, SoC, system-on-chip, unordered networks
Abstract

The inclusion of programmable logic cores in modern SoC motivates the need for an access network to make full use of this resource. The programmable nature of these cores removes the requirement of input/output ordering on this access network. Theoretical work on a class of unordered networks called concentrators has shown that as these networks become large, they have a lower cost than ordered or permutation networks. However, currently known constructions of concentrator networks are not lower cost than permutation networks for the entire range of networks of the size required for SoC. This paper demonstrates the differences in the cost and depth of concentrator and permutation networks. It also presents a new construction of a concentrator network that has lower cost and depth than a permutation network for all configurations.

URLhttp://dx.doi.org/10.1109/ISCAS.2005.1464520
DOI10.1109/ISCAS.2005.1464520

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