Design, synthesis, and test of networks on chips

TitleDesign, synthesis, and test of networks on chips
Publication TypeJournal Article
Year of Publication2005
AuthorsPande, P. P., C. Grecu, A. Ivanov, R. Saleh, and G. De Micheli
JournalIEEE Design & Test of Computers
Volume22
Pagination404–413
ISSN0740-7475
Abstract

For networks on chips to succeed as the next generation of on- chip interconnect, researchers must solve the major problems involved in designing, implementing, verifying, and testing them. This article surveys the latest NoC architectures, methods, and tools and shows what must happen to make NoCs part of a viable future.

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