Evaluation of MP-SoC interconnect architectures: a case study

TitleEvaluation of MP-SoC interconnect architectures: a case study
Publication TypeConference Paper
Year of Publication2004
AuthorsPande, P. P., C. Grecu, M. Jones, A. Ivanov, and R. Saleh
Conference NameSystem-on-Chip for Real-Time Applications, 2004.Proceedings. 4th IEEE International Workshop on
Pagination253 - 256
Date Publishedjul.
Keywordsbutterfly fat-tree topology, embedded processors, formal evaluation, integrated circuit design, IP blocks, mesh topology, MP-SoC interconnect architectures, multiprocessor interconnection networks, parallel architectures, performance evaluation, performance metrics, SoC design, system on chip, system-on-chip

Multiprocessor (MP-SoC) platforms are emerging as the latest trend in SoC design. These MP-SoCs consist of a large number of IP blocks in the form of functionally heterogeneous embedded processors. In this design paradigm, IP blocks need to be integrated using a structured interconnect template, for example, according to high-performance parallel computing architectures. A formal evaluation process is required before adopting a specific parallel architecture to SoC domain. Here, we propose an evaluation methodology based on performance metrics that include latency, throughput and silicon area requirements. As a case study, we present the results of such an evaluation for two MP-SoC interconnect topologies, i.e., the mesh and the butterfly fat-tree (BFT). This evaluation methodology can be extended to any other SoC interconnect topology without loss of generality.


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