Placement and routing for FPGA architectures supporting wide shallow memories

TitlePlacement and routing for FPGA architectures supporting wide shallow memories
Publication TypeConference Paper
Year of Publication2003
AuthorsOldridge, S. W., and S. J. E. Wilton
Conference NameField-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on
Pagination154 - 161
Date Publisheddec.
Keywordscircuit CAD, embedded memories, field programmable gate array architectures, field programmable gate arrays, FPGA architectures, FPGA placement, FPGA routing, integrated memory circuits, memory architecture, memory resources, network routing, routing algorithms, routing resources, standard memory architectures, switch block configuration memory, system sized circuits, wide shallow memories

Today, FPGAs are being used to implement large, system-sized circuits. Systems often require significant memory resources, and vendors have responded to these needs by embedding block memories onto their FPGAs. In we presented an architecture designed to efficiently support the need for wide shallow memories on an FPGA by allowing switch block configuration memory to be read and written by the user circuit. This FPGA presents a unique placement and routing problem, since the embedded memories displace routing resources in switch blocks. In this paper, we present novel place and route algorithms for an FPGA containing these wide shallow memories. Using these tools, a comparison between FPGAs containing switch block memories and those containing standard memory architectures shows that switch block memory based solutions are 22% smaller and 40% faster, despite their overhead.


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