Processor-Level Selective Replication

TitleProcessor-Level Selective Replication
Publication TypeConference Paper
Year of Publication2007
AuthorsNakka, N., K. Pattabiraman, and R. Iyer
Conference NameDependable Systems and Networks, 2007. DSN '07. 37th Annual IEEE/IFIP International Conference on
Pagination544 -553
Date Publishedjun.
Keywordsapplication-aware, error analysis, error detection, fault-injection, processor-level selective replication, redundancy, redundant hardware, static analysis
Abstract

We propose a processor-level technique called selective replication, by which the application can choose where in its application stream and to what degree it requires replication. Recent work on static analysis and fault-injection-based experiments on applications reveals that certain variables in the application are critical to its crash- and hang-free execution. If it can be ensured that only the computation of these variables is error-free, then a high degree of crash/hang coverage can be achieved at a low performance overhead to the application. The selective replication technique provides an ideal platform for validating this claim. The technique is compared against complete duplication as provided in current architecture-level techniques. The results show that with about 59% less overhead than full duplication, selective replication detects 97% of the data errors and 87% of the instruction errors that were covered by full duplication. It also reduces the detection of errors benign to the final outcome of the application by 17.8% as compared to full duplication.

URLhttp://dx.doi.org/10.1109/DSN.2007.75
DOI10.1109/DSN.2007.75

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