An embedded autonomous scan-based results analyzer (EARA) for SoC cores

TitleAn embedded autonomous scan-based results analyzer (EARA) for SoC cores
Publication TypeConference Paper
Year of Publication2003
AuthorsNahvi, M., and A. Ivanov
Conference NameVLSI Test Symposium, 2003. Proceedings. 21st
Pagination293 - 298
Date Publishedapr.
KeywordsATE resources, automatic test equipment, boundary scan testing, circuit simulation, DAST hierarchy, dedicated autonomous scan-based testing, EARA, embedded autonomous results analyzer, embedded blocks, integrated circuit design, integrated circuit testing, logic design, logic simulation, logic testing, on-chip test stimulus/results comparison, SoC cores, system-on-chip, test data communication, test data control, test data observation
Abstract

Relying solely upon external ATE resources for scan test in complex SoC designs is increasingly difficult. In this work, we develop the concept and implementation of an embedded autonomous results analyzer (EARA) to be used in our modified dedicated autonomous scan-based testing (DAST) methodology. DAST introduces hierarchy and separates the functionality of ATE resources into two distinctive classes: a) test data communication; and b) test data control and observation. Consequently, test data control/observation functions are transferred to embedded blocks. In this work, we extend DAST to include the sending of expected test results along with the test stimulus to enable on-chip comparison. We present implementation results of EARA when applied to a number of SoC benchmarks.

URLhttp://dx.doi.org/10.1109/VTEST.2003.1197666
DOI10.1109/VTEST.2003.1197666

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