A high-speed low-energy dynamic PLA using an input-isolation scheme

TitleA high-speed low-energy dynamic PLA using an input-isolation scheme
Publication TypeConference Paper
Year of Publication2006
AuthorsMolavi, R., S. Mirabbasi, and R. Saleh
Conference NameCircuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Pagination4 pp. -2888
Keywords0.18 micron, CMOS logic circuits, dynamic NOR architecture, flip-flops, input-isolation, latch-based sense amplifier, low-power electronics, NOR circuits, PLA, programmable logic arrays, structured logic arrays

Recently, there has been renewed interest in structured logic arrays due to a number of inherent advantages. However, before they will be more widely adopted, structured logic arrays must be able to compete with standard ASIC designs. This paper proposes a CMOS PLA based on a dynamic NOR architecture that uses an input-isolation technique along with a latch-based sense amplifier to achieve both high operating speed and low-energy consumption. The proposed architecture is designed and simulated in a 0.18mum CMOS technology. It improves the delay by 10% compared with the fastest reported PLA. It also achieves the lowest power-delay product of all other reported dynamic PLAs


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