A Novel Active Decoupling Capacitor Design in 90nm CMOS

TitleA Novel Active Decoupling Capacitor Design in 90nm CMOS
Publication TypeConference Paper
Year of Publication2007
AuthorsMeng, X., K. Arabif, and R. Saleh
Conference NameCircuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Pagination657 -660
Date Publishedmay.
Keywords1 V, 3.0 mW, 90 nm, active decoupling capacitor design, capacitors, circuit noise, CMOS, CMOS integrated circuits, electrostatic discharge reliability, higher operating frequency, integrated circuit design, interference suppression, lower supply voltage, on-chip decoupling capacitors, power supply circuits, power supply noise reduction, reliability, thin-oxide gate leakage

On-chip decoupling capacitors (decaps) are generally used to reduce power supply noise. Passive decap designs are reaching their limits in 90nm CMOS technology due to higher operating frequency, lower supply voltage, increased concerns on electrostatic discharge (ESD) reliability and thin-oxide gate leakage. In this paper, a novel active decap design is proposed to provide better noise reduction than the passive decaps. The active decap is analyzed for ESD reliability and process/temperature variation adaptability. It is implemented in a 1.0V-core 90nm process with a total area of 0.168mm2 and standby power of 3.0mW.


a place of mind, The University of British Columbia

Electrical and Computer Engineering
2332 Main Mall
Vancouver, BC Canada V6T 1Z4
Tel +1.604.822.2872
Fax +1.604.822.5949

Emergency Procedures | Accessibility | Contact UBC | © Copyright 2020 The University of British Columbia