Novel decoupling capacitor designs for sub-90nm CMOS technology

TitleNovel decoupling capacitor designs for sub-90nm CMOS technology
Publication TypeConference Paper
Year of Publication2006
AuthorsMeng, X., K. Arabi, and R. Saleh
Conference NameQuality Electronic Design, 2006. ISQED '06. 7th International Symposium on
Pagination6 pp. -271
Date Publishedmar.
Keywords90 nm, capacitors, CMOS integrated circuits, CMOS technology, cross coupled design, decoupling capacitors, electrostatic discharge, integrated circuit design, integrated circuit reliability, leakage currents, NMOS devices, power supply noise, thin-oxide gate leakage, transient response

On-chip decoupling capacitors are generally used to reduce power supply noise. Traditional decoupling capacitor designs using NMOS devices may no longer be suitable for 90nm CMOS technology due to increased concerns on thin-oxide gate leakage and electrostatic discharge (ESD) reliability. A cross coupled design for standard cells have recently been proposed to address the ESD issue. In this paper, three modifications of the cross coupled design are introduced and the tradeoffs among ESD performance, transient response and gate leakage are analyzed. As shown here, the modifications offer designers greater flexibility in decoupling capacitor design for 90nm and below


a place of mind, The University of British Columbia

Electrical and Computer Engineering
2332 Main Mall
Vancouver, BC Canada V6T 1Z4
Tel +1.604.822.2872
Fax +1.604.822.5949

Emergency Procedures | Accessibility | Contact UBC | © Copyright 2021 The University of British Columbia