A system-level stochastic circuit generator for FPGA architecture evaluation

TitleA system-level stochastic circuit generator for FPGA architecture evaluation
Publication TypeConference Paper
Year of Publication2008
AuthorsMark, C., A. Shui, and S. Wilton
Conference NameICECE Technology, 2008. FPT 2008. International Conference on
Pagination25 -32
Date Publisheddec.
Keywordsfield programmable gate arrays, FPGA architecture evaluation, network synthesis, SoC circuits, system-level stochastic circuit generator, system-on-chip, system-on-chip design flow
Abstract

We describe a stochastic circuit generator that can be used to automatically create benchmark circuits for use in FPGA architecture studies. The circuits consist of a hierarchy of interconnected modules, reflecting the structure of circuits designed using a system-on-chip design flow. Within each level of hierarchy, modules can be connected in a bus, star, or dataflow configuration. Our circuit generator is calibrated based on a careful study of existing SoC circuits. We compare our circuits to those generated by previous circuit generators, and characterize our circuits with respect to the type of network used to connect modules.

URLhttp://dx.doi.org/10.1109/FPT.2008.4762362
DOI10.1109/FPT.2008.4762362

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