An integrated functional tester for CMOS logic

TitleAn integrated functional tester for CMOS logic
Publication TypeConference Paper
Year of Publication1993
AuthorsLow, W., and A. Ivanov
Conference NameElectrical and Computer Engineering, 1993. Canadian Conference on
Pagination453 -456 vol.1
Date Publishedsep.
Keywords1.2 mum, 5 mm, 6 mm, 7 mm, 8-bit instructions, bandwidth requirements, CMOS integrated circuits, CMOS logic, die size, digital standard cells, dual metal layer CMOS process, edge resolutions, encoded, encoding, format memory, functional analysis, functional tester chip, functional tester system, input window comparison, integrated circuit testing, integrated functional tester, logic testing, on-the-fly format switching, output waveform formatting, programmability, required timing, test vector, wave formatting circuit
Abstract

This paper presents the architecture of a functional tester system based on a functional tester chip (FTC) featuring per-pin programmability, output waveform formatting (NR, RC, RH, and RL), input window comparison and on-the-fly format switching. Waveforms are encoded using a set of simple 8-bit instructions. The bandwidth requirements of each channel is 8 bits per test vector. A four-channel FTC implemented using digital standard cells, with a 1.2 micron dual metal layer CMOS process, has a die size of 7 times;6 mm2 (core: 6 times;5 mm 2). Each channel occupies approximately 17% of the core area. Almost half the channel area is used by the format memory which provides a cache of the required timing and formats for a given test. Preliminary results based on measurements from an early version of the wave formatting circuit suggest that edge resolutions of at least 1.5 ns are possible

URLhttp://dx.doi.org/10.1109/CCECE.1993.332196
DOI10.1109/CCECE.1993.332196

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