The architecture of dual-mode FPGA embedded system blocks

TitleThe architecture of dual-mode FPGA embedded system blocks
Publication TypeConference Paper
Year of Publication2002
AuthorsLin, E., and S. J. E. Wilton
Conference NameCustom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002
Pagination67 - 70
Keywords16 bit, dual-mode FPGA, embedded system blocks, embedded systems, field programmable gate arrays, logic CAD, memory architecture, memory architecture parameters, optimum memory architecture, unused on-chip memories
Abstract

Recently, it has been shown that unused on-chip memories can be valuable when they are used to implement logic. This paper explores how different memory architecture parameters affect its ability to implement logic in dual-mode FPGA embedded system blocks. It is shown that the optimum memory architecture has a depth of 32 or 64 words, and that each word should contain 16 bits.

URLhttp://dx.doi.org/10.1109/CICC.2002.1012768
DOI10.1109/CICC.2002.1012768

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