Directional and single-driver wires in FPGA interconnect

TitleDirectional and single-driver wires in FPGA interconnect
Publication TypeConference Paper
Year of Publication2004
AuthorsLemieux, G., E. Lee, M. Tom, and A. Yu
Conference NameField-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on
Pagination41 - 48
Date Publisheddec.
KeywordsAltera, circuit design, directional driver wires, field programmable gate arrays, FPGA architectures, FPGA interconnect, integrated circuit design, integrated circuit interconnections, interconnect wire, physical wire length shrinkage, single-driver wires, switch loading, wiring capacitance, Xilinx

Modern FPGA architectures from Altera and Xilinx have shifted away from allowing multiple drivers to connect to each interconnect wire. This work advocates the need for this shift to single-driver wiring by investigating the necessary architectural and circuit design changes. When single-driver wiring is used, area improves by 25%, delay improves by 9%, and area-delay improves by 32% compared to bidirectional wiring. Wiring capacitance is reduced by 37% due to reduced switch loading and physical wire length shrinkage. Furthermore, it is shown that larger circuits tend to realize larger savings. No significant CAD tool changes are needed.


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