A multi-FPGA application-specific architecture for accelerating a floating point Fourier Integral Operator

TitleA multi-FPGA application-specific architecture for accelerating a floating point Fourier Integral Operator
Publication TypeConference Paper
Year of Publication2008
AuthorsLee, J., L. Shannon, M. J. Yedlin, and G. F. Margrave
Conference NameApplication-Specific Systems, Architectures and Processors, 2008. ASAP 2008. International Conference on
Pagination197 -202
Date Publishedjul.
Keywordsfast Fourier transform, fast Fourier transforms, field programmable gate arrays, floating point computing elements, Fourier integral operator, FPGAs, multiple FPGAs
Abstract

Many complex systems require the use of floating point arithmetic that is exceedingly time consuming to perform on personal computers. However, floating point operators are also hardware resource intensive and require longer latencies than fixed point operators to complete. Due to the reduced logic density of FPGAs relative to ASICs, it is often only possible to accelerate a portion of a floating point application in hardware. This paper presents an application-specific architecture for the hardware acceleration of a complete Fourier Integral Operator (FIO) kernel used in seismic imaging on a multi-FPGA platform. The design utilizes several floating point computing elements (CEs) to calculate the FIO kernel in parallel stages on multiple FPGAs. A detailed study of floating point CEs, including a Fast Fourier Transform (FFT) CE, and a complete FIO prototype implementation on the BEE2 platform is described. The prototype implementation has a 12.4x increase in throughput over an optimized software implementation, and a predicted 15.8x increase in throughput on the BEE3 platform.

URLhttp://dx.doi.org/10.1109/ASAP.2008.4580178
DOI10.1109/ASAP.2008.4580178

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