Register file architecture optimization in a coarse-grained reconfigurable architecture

TitleRegister file architecture optimization in a coarse-grained reconfigurable architecture
Publication TypeConference Paper
Year of Publication2005
AuthorsKwok, Z., and S. J. E. Wilton
Conference NameField-Programmable Custom Computing Machines, 2005. FCCM 2005. 13th Annual IEEE Symposium on
Pagination35 - 44
Date Publishedapr.
KeywordsADRES architecture, coarse-grained reconfigurable architecture, file organisation, optimisation, reconfigurable architectures, register file architecture optimization
Abstract

This paper investigates the impact of the local and global register file architecture on a reconfigurable system based on the ADRES architecture. The register files consume a significant amount of area on the reconfigurable device, and their architecture has a strong impact on the performance. We found that the global registers should be tightly connected to as many functional units as possible, while the connection of the local register files to their neighbours is less critical. We found that the global register file should contain between 12 and 16 registers, while each local register file should only contain one or two registers. We used these results to propose a new architecture that has between 60% and 95% higher performance per unit area compared to the original architecture over the set of benchmarks.

URLhttp://dx.doi.org/10.1109/FCCM.2005.58
DOI10.1109/FCCM.2005.58

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