Fuzzy biasless simulated evolution for multiobjective VLSI placement

TitleFuzzy biasless simulated evolution for multiobjective VLSI placement
Publication TypeConference Paper
Year of Publication2002
AuthorsKhan, J. A., S. M. Sait, and M. R. Minhas
Conference NameEvolutionary Computation, 2002. CEC '02. Proceedings of the 2002 Congress on
Pagination1642 -1647
Keywordsadaptive bias scheme, algorithm run-time, biasless selection scheme, circuit layout CAD, circuit optimisation, circuit simulation, error compensation, evolutionary computation, fuzzy biasless simulated evolution, fuzzy logic, goodness calculation error compensation, goodness measure, heuristic programming, imprecise design information, integrated circuit layout, iteration, iterative methods, multi-objective VLSI placement, poorly placed cell selection, probabilistic selection, problem instances, search problems, selection bias parameter, simulated evolution algorithm, solution quality, solution subspace searching, VLSI
Abstract

In each iteration of a simulated evolution (SE) algorithm for VLSI placement, poorly placed cells are selected probabilistically, based on a measure known as 'goodness'. To compensate for the error in the goodness calculation (and to maintain the number of selected cells within some limit), a parameter known as 'bias' is used, which has major impact on the algorithm's run-time and on the quality of the solution subspace searched. However, it is difficult to select the appropriate value of this selection bias because it varies for each problem instance. In this paper, a biasless selection scheme for the SE algorithm is proposed. This scheme eliminates the human interaction needed in the selection of the bias value for each problem instance. Due to the imprecise nature of the design information at the placement stage, fuzzy logic is used in all stages of the SE algorithm. The proposed scheme was compared with an adaptive bias scheme and was always able to achieve better solutions

URLhttp://dx.doi.org/10.1109/CEC.2002.1004488
DOI10.1109/CEC.2002.1004488

a place of mind, The University of British Columbia

Electrical and Computer Engineering
2332 Main Mall
Vancouver, BC Canada V6T 1Z4
Tel +1.604.822.2872
Fax +1.604.822.5949
Email:

Emergency Procedures | Accessibility | Contact UBC | © Copyright 2021 The University of British Columbia