Power Reduction of On-Chip Serial Links

TitlePower Reduction of On-Chip Serial Links
Publication TypeConference Paper
Year of Publication2007
AuthorsKedia, A., and R. Saleh
Conference NameCircuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Pagination865 -868
Date Publishedmay.
Keywordsbit ordering, integrated circuit interconnections, low-power electronics, on-chip serial links, power reduction, reduced design complexity, reduced routing congestion, reduced switching activity, tree searching
Abstract

On-chip serial links to replace standard buses for global communication have been the subject of a number of recent investigations. The main reason for considering serial links is to reduce routing congestion and design complexity. However, the serialization of parallel data may actually increase the power dissipation due to increased switching activity. This paper describes a new bit ordering technique to reduce switching activity on serial links, assuming that the statistical data of the parallel bus traces are known in advance. The method reduces the switching activity by an average of 40% 50% compared to random bit ordering.

URLhttp://dx.doi.org/10.1109/ISCAS.2007.378043
DOI10.1109/ISCAS.2007.378043

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