Tradeoffs in two-level on-chip caching

TitleTradeoffs in two-level on-chip caching
Publication TypeConference Paper
Year of Publication1994
AuthorsJouppi, N. P., and S. J. E. Wilton
Conference NameComputer Architecture, 1994., Proceedings the 21st Annual International Symposium on
Pagination34 -45
Date Publishedapr.
Keywordsassociativity, buffer storage, capacity, memory architecture, on-chip caching, replacement policy, set-associative second level, storage management, two-level cache configurations, two-level exclusive caching, two-level on-chip caching

The performance of two-level on-chip caching is investigated for a range of technology and architecture assumptions. The area and access time of each level of cache is modeled in detail. The results indicate that for most workloads, two-level cache configurations (with a set-associative second level) perform marginally better than single-level cache configurations that require the same chip area once the first-level cache sizes are 64 KB or larger. Two-level configurations become even more important in systems with no off-chip cache and in systems in which the memory cells in the first-level caches are multiported and hence larger than those in the second-level cache. Finally, a new replacement policy called two-level exclusive caching is introduced. Two-level exclusive caching improves the performance of two-level caching organizations by increasing the effective associativity and capacity


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