Dynamic testability measures for ATPG

TitleDynamic testability measures for ATPG
Publication TypeJournal Article
Year of Publication1988
AuthorsIvanov, A., and V. K. Agarwal
JournalComputer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Pagination598 -608
Date Publishedmay.
Keywordsautomatic test pattern generation, automatic testing, benchmark circuits, dynamic testability measures, electronic equipment testing, FAN, fault coverage, heuristics, IC testing, integrated circuit testing, logic testing, PODEM, random processes, random-pattern, test-set generation

Two automatic test pattern generation (ATPG) algorithms, PODEM and FAN, use heuristics that rely on testability measures (TMs). The use of random-pattern (probabilistic) TMs in these heuristics has already been proposed and investigated. The types of TMs proposed for such use are static. Static TMs (STMs) become increasingly unjustifiable as the search for a test pattern progresses. Dynamic TMs (DTMs) are introduced as a method to overcome the deficiency in the quality of STMs while still observing linear time and storage constraints. Based on results from several experiments, test-set generation strategy is devised that utilizes the advantages of both STMs and DTMs. From the experiments performed on benchmark circuits, compared to the strategy wherein only STMs are used to attain a given fault coverage, the proposed strategy requires considerably less CPU time to obtain a test set which attains the same fault coverage


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