Clock verification in the presence of IR-drop in the power distribution network

TitleClock verification in the presence of IR-drop in the power distribution network
Publication TypeConference Paper
Year of Publication1999
AuthorsHussain, S. Z., S. Rochel, D. OVERHAUSER, and R. Saleh
Conference NamePROCEEDINGS OF THE IEEE 1999 CUSTOM INTEGRATED CIRCUITS CONFERENCE
Pagination437-440
PublisherIEEE Solid States Circuits Soc
Conference Location345 E 47TH ST, NEW YORK, NY 10017 USA
ISBN Number0-7803-5443-5
Abstract

Clock nets are the most important circuits in high-speed digital systems. The design of clock circuitry and the quality of the clock signal directly impacts the performance of a VLSI chip. Clock verification requires high accuracy and is typically performed using circuit simulators. In high-performance deep-submicron digital circuits, clocks are running at higher frequencies and are driving more gates than ever, thus presenting a higher load on the power distribution network with the potential of substantial IR-drop. However, as IR-drop is a full-chip phenomenon, circuit simulation is extremely time consuming. In this paper, we present a loosely coupled iterative technique for clock verification in the presence of full-chip dynamic IR-drop. The degradation in the clock signal due to dynamic IR-drop is demonstrated on a small example as well as upon a large chip. In addition, we also discuss risks associated with assuming a static IR-drop budget upon clock propagation.

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