Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications

TitleDomain-Specific Hybrid FPGA: Architecture and Floating Point Applications
Publication TypeConference Paper
Year of Publication2007
AuthorsHo, C. H., C. W. Yu, P. H. W. Leong, W. Luk, and S. J. E. Wilton
Conference NameField Programmable Logic and Applications, 2007. FPL 2007. International Conference on
Pagination196 -201
Date Publishedaug.
Keywordsbit-oriented operations, control logic, domain-specific coarse-grained units, domain-specific hybrid FPGA, domain-specific information, field programmable gate arrays, floating point applications, floating point arithmetic, reconfigurable architectures, reconfigurable logic

This paper presents a novel architecture for domain-specific FPGA devices. This architecture can be optimised for both speed and density by exploiting domain-specific information to produce efficient reconfigurable logic with multiple granularity. In the reconfigurable logic, general-purpose fine-grained units are used for implementing control logic and bit-oriented operations, while domain-specific coarse-grained units and heterogeneous blocks are used for implementing datapaths; the precise amount of each type of resources can be customised to suit specific application domains. Issues and challenges associated with the design flow and the architecture modelling are addressed. Examples of the proposed architecture for speeding up floating point applications are illustrated. Current results indicate that the proposed architecture can achieve 2.5 times improvement in speed and 18 times reduction in area on average, when compared with traditional FPGA devices on selected floating point benchmark circuits.


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