Design considerations for Sub-mW RF CMOS low-noise amplifiers

TitleDesign considerations for Sub-mW RF CMOS low-noise amplifiers
Publication TypeJournal Article
Year of Publication2007
AuthorsHo, D., and S. Mirabbasi
Journal2007 Canadian Conference on Electrical and Computer Engineering, Vols 1-3
Pagination376–380
ISSN0840-7789
Abstract

Design considerations for sub-mW fully integrated narrow-band RF CMOS low-noise amplifiers (LNAs) are presented. The impacts of device-level properties and biasing on gain, noise, linearity, and power consumption of an LNA are discussed. Based on the design trade-offs discussed in the paper, a cascode LNA is designed and simulated in a standard 90nm CMOS process to operate in the 2.4GHz band. The LNA achieves a voltage gain of 22.7dB, NF of 2.8dB, IIP3 of +5.14dBm, and P1dB of -10dBm, while consuming 943 mu W from a 1V supply.

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