Low complexity architecture for exponentiation in GF(2m)

TitleLow complexity architecture for exponentiation in GF(2m)
Publication TypeJournal Article
Year of Publication1992
AuthorsHasan, M. A., and V. K. Bhargava
JournalElectronics Letters
Volume28
Pagination1984 -1986
Date Publishedoct.
ISSN0013-5194
Keywordscryptography, cryptosystem, digital arithmetic, finite field exponentiation, Galois field, GF(2 m), multiplying circuits, parallel architectures, pipeline bit-serial multiplier architecture, pipeline processing, VLSI implementation
Abstract

A pipeline bit-serial multiplier architecture for the Galois field GF(2m) is presented. A structure for finite field exponentiation is developed based on the multiplier. The structure is regular, area efficient and suitable for VLSI implementation for large fields.

URLhttp://dx.doi.org/10.1049/el:19921272
DOI10.1049/el:19921272

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