Bit-serial systolic divider and multiplier for finite fields GF(2 m)

TitleBit-serial systolic divider and multiplier for finite fields GF(2 m)
Publication TypeJournal Article
Year of Publication1992
AuthorsHasan, M. A., and V. K. Bhargava
JournalComputers, IEEE Transactions on
Volume41
Pagination972 -980
Date Publishedaug.
ISSN0018-9340
Keywordsbit-serial division, bit-serial systolic multiplier, chip fabrication, circuit complexity, computational complexity, control signal, digital arithmetic, dividing circuits, finite fields, multiplying circuits, systolic structure, time complexity
Abstract

A systolic structure for bit-serial division over the field GF(2 m) is developed. Consideration is given to avoid global data communications and dependency of the time step duration on m. This is important for applications where the value of m is large. The divider requires only three basic processors and one simple control signal and its circuit and time complexities are proportional to m2 and m, respectively. It does not depend on the irreducible polynomial and can be expanded easily. Moreover, with m additional simple processors, a bit-serial systolic multiplier is developed which uses part of the divider structure. This is advantageous from the implementation point of view, as both the divider and multiplier can be fabricated on a single chip, resulting in a reduction of area

URLhttp://dx.doi.org/10.1109/12.156540
DOI10.1109/12.156540

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