Fast configuration of an energy-efficient branch predictor

TitleFast configuration of an energy-efficient branch predictor
Publication TypeConference Paper
Year of Publication2006
AuthorsHallschmid, P., and R. Saleh
Conference NameEmerging VLSI Technologies and Architectures, 2006. IEEE Computer Society Annual Symposium on
Pagination6 pp.
Date Publishedmar.
Keywordsapplication specific instruction set processors, application specific integrated circuits, automatic configuration, energy-efficient branch predictor, instruction sets, microprocessor chips, pattern history table
Abstract

Recent research in the area of application specific instruction-set processors (ASIPs) has focused on automatic configuration. In this paper, we propose a novel approach for selecting the size of the branch predictor pattern history table (PHT) to reduce the overall power dissipation for a specific application. This approach uses a fast configuration approach that dynamically measures aliasing for all PHT sizes in parallel and then uses a cost function that relates aliasing to power dissipation. Results show that by configuring the PHT using our approach, the overall power reduction closely matches that achievable with a "perfect" configuration

URLhttp://dx.doi.org/10.1109/ISVLSI.2006.44
DOI10.1109/ISVLSI.2006.44

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