Title | Routing architecture optimizations for high-density embedded programmable IP cores |
Publication Type | Journal Article |
Year of Publication | 2005 |
Authors | Hallschmid, P., and S. J. E. Wilton |
Journal | Very Large Scale Integration (VLSI) Systems, IEEE Transactions on |
Volume | 13 |
Pagination | 1320 - 1324 |
Date Published | nov. |
ISSN | 1063-8210 |
Keywords | channel widths, circuit optimisation, embedded systems, field-programmable gate arrays, high-density embedded programmable IP cores, integrated circuit design, logic block pin placement, logic design, programmable logic devices, rectangular programmable logic cores, routing architecture optimization, switch block |
Abstract | Programmable logic cores differ from stand-alone field-programmable gate arrays in that they can take on a variety of shapes and sizes. With this in mind, we investigate the detailed routing architecture of rectangular programmable logic cores. We quantify the effects of having different X and Y channel capacities and show that the optimum ratio between the X and Y channel widths for a rectangular core is between 1.2 and 1.5. We also present a new switch block family optimized for rectangular cores. Further, we quantify the effects of logic block pin placement. Compared with a simple extension of an existing switch block, our new architecture leads to a density improvement of up to 11.9%. Finally, we show that, if the channel width, switch block, and pin placement are chosen carefully, then the penalty for using a rectangular core (compared to a square core with the same logic capacity) is small; for a core with an aspect ratio of 2:1, the area penalty is 1.6% and the speed penalty is 3.8%. |
URL | http://dx.doi.org/10.1109/TVLSI.2005.859561 |
DOI | 10.1109/TVLSI.2005.859561 |