The NUMAchine multiprocessor

TitleThe NUMAchine multiprocessor
Publication TypeConference Paper
Year of Publication2000
AuthorsGrindley, R., T. Abdelrahman, S. Brown, S. Caranci, D. DeVries, B. Gamsa, A. Grbic, M. Gusat, R. Ho, O. Krieger, G. Lemieux, K. Loveless, N. Manjikian, P. McHardy, S. Srbljic, M. Stumm, Z. Vranesic, and Z. Zilic
Conference NameParallel Processing, 2000. Proceedings. 2000 International Conference on
Pagination487 -496
Keywordsdirectory-based cache coherence protocol, large-scale multiprocessors, multiprocessing systems, multiprocessors, NUMAchine multiprocessor, parallel architectures, performance, prototype hardware, ring-based interconnect, sequential consistency
Abstract

Small-scale multiprocessors are becoming increasingly economical and common, whereas larger multiprocessors continue to have higher per-node costs. The NUMAchine multiprocessor project seeks to make large-scale multiprocessors more economical while maintaining high performance by exploring architectural and hardware features for low-cost, modular multiprocessors. To demonstrate our approach, we have implemented a prototype system that is scalable to 128 processors. An efficient directory-based cache coherence protocol exploits our hierarchical ring-based interconnect and supports sequential consistency. This paper documents the design choices and the resulting performance of the system using both simulation results and measurements on the prototype hardware

URLhttp://dx.doi.org/10.1109/ICPP.2000.876165
DOI10.1109/ICPP.2000.876165

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