BIST for network-on-chip interconnect infrastructures

TitleBIST for network-on-chip interconnect infrastructures
Publication TypeConference Paper
Year of Publication2006
AuthorsGrecu, C., P. Pande, A. Ivanov, and R. Saleh
Conference NameVLSI Test Symposium, 2006. Proceedings. 24th IEEE
Pagination6 pp. -35
Date Publishedapr.
KeywordsBIST, bootstrap, built-in self test, coupled circuits, crosstalk, crosstalk effects, data transport mechanism, high-level fault model, inter switch links, inter-wire coupling, interconnect infrastructures, network-on-chip, switched networks
Abstract

In this paper, we present a novel built-in self-test methodology for testing the inter-switch links of network-on-chip (NoC) based chips. This methodology uses a high-level fault model that accounts for crosstalk effects due to inter-wire coupling. The novelty of our approach lies in the progressive reuse of the NoC infrastructure to transport test data to its own components under test in a bootstrap manner, and in extensively exploiting the inherent parallelism of the data transport mechanism to reduce the test time and implicitly the test cost

URLhttp://dx.doi.org/10.1109/VTS.2006.22
DOI10.1109/VTS.2006.22

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