A scalable communication-centric SoC interconnect architecture

TitleA scalable communication-centric SoC interconnect architecture
Publication TypeConference Paper
Year of Publication2004
AuthorsGrecu, C., P. P. Pande, A. Ivanov, and R. Saleh
Conference NameQuality Electronic Design, 2004. Proceedings. 5th International Symposium on
Pagination343 - 348
Keywordsbus-based functional interconnect, butterfly fat-tree, delays, floorplan, global synchronization, heterogeneous intellectual property blocks, integrated circuit interconnections, integrated circuit layout, network routing, nonscalable global wire delays, overall timing closure, routing architecture, scalable communication-centric architecture, SoC interconnect architecture, structured interconnect template, system-on-chip, timing, ultra deep submicron technologies
Abstract

System on Chip (SoC) design in the forthcoming billion-transistor era will involve the integration of numerous heterogeneous semiconductor intellectual property (IP) blocks. Some of the main problems in the ultra deep submicron technologies arise from nonscalable global wire delays, failure to achieve global synchronization and difficulties associated with nonscalable bus-based functional interconnect. These problems can be dealt with by using a structured interconnect template to design future SoCs. Recently, we introduced the butterfly fat-tree as an overall interconnect architecture, where IPs reside at the leaves of the tree and switches at its vertices. Here, we analyze this architecture with a particular focus on achieving overall timing closure. The only global wires in this routing architecture are the inter-switch wires and the delays in these global wires can be predicted at the initial stages of design cycle. Our analysis shows that the inter-switch wire delay in the networked SoC can be always designed to fit within one clock cycle, regardless of the system size. We contrast the analysis for our network with that of a bus-based architecture. For the latter, we illustrate how the interconnect delay and system size are interrelated, thereby limiting the number of IP blocks that can be connected by a bus.

URLhttp://dx.doi.org/10.1109/ISQED.2004.1283698
DOI10.1109/ISQED.2004.1283698

a place of mind, The University of British Columbia

Electrical and Computer Engineering
2332 Main Mall
Vancouver, BC Canada V6T 1Z4
Tel +1.604.822.2872
Fax +1.604.822.5949
Email:

Emergency Procedures | Accessibility | Contact UBC | © Copyright 2020 The University of British Columbia