A 2B parallel 1.25 Gb/s interconnect I/O interface with self-configurable link and plesiochronous clocking

TitleA 2B parallel 1.25 Gb/s interconnect I/O interface with self-configurable link and plesiochronous clocking
Publication TypeConference Paper
Year of Publication1999
AuthorsGotoh, K., H. Tamura, H. Takauchi, T. S. Cheung, W. Gai, Y. Koyanagi, R. Schober, R. Sastry, and F. Chen
Conference NameSolid-State Circuits Conference, 1999. Digest of Technical Paper s. ISSCC. 1999 IEEE International
Pagination180 -181
Keywords1.25 Gbit/s, 2 B, 20 m, 7.7 ns, clocks, deskew circuitry, differential partial-response detection receiver, I/O transceiver, inter-wiring skew, interconnect I/O interface, latency, logic sequencer, multiple I/O links, multiprocessing systems, parallel bandwidth, partial response channels, phase-interpolator-based clock recovery, plesiochronous clocking, power consumption, receiver clock phase, scalable multiprocessor systems, self-configurable link, skin-effect cable loss, transceivers, twisted pair cables, twisted-pair cables, wiring

An I/O transceiver for scalable multiprocessor systems with 1.25 Gb/s parallel bandwidth and 7.7 ns latency performs as a plesiochronous link and compensates for skin-effect cable loss and inter-wiring skew across 20 m cable connections. Phase-interpolator-based clock recovery integrates multiple I/O links that can tolerate slight differences in frequencies between incoming and internal reference clocks. A differential partial-response detection (DPRD) receiver ensures low latency equalization for skin-effect cable loss of up to 10 dB. The receivers are equipped with deskew circuitry to tolerate up to 6.4 ns inter-wiring skew for 20 data bits. The data rate, driver output level, and receiver clock phase are adjusted automatically by a logic sequencer, basic control, which maximizes data rate and minimizes power consumption without external manual adjustment, adapting from onboard PCB traces to 20 m twisted-pair cables


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