VHDL design of an ATM switch

TitleVHDL design of an ATM switch
Publication TypeConference Paper
Year of Publication1995
AuthorsGilderson, J., F. El-Guibaly, and V. K. Bhargava
Conference NameCommunications, Computers, and Signal Processing, 1995. Proceedings. IEEE Pacific Rim Conference on
Pagination100 -103
Date Publishedmay.
Keywordsasynchronous transfer mode, ATM layer switch, ATM management cells, ATM signalling cells, ATM switch, ATM switching system, hardware description languages, performance optimisation, protocol model, standards documents, telecommunication computing, telecommunication network management, telecommunication signalling, telecommunication standards, telecommunication switching, VHDL design
Abstract

An ATM switch must be capable of not only routing a user data cell from an input to an output port, it must also be capable of interpreting and processing ATM signalling and management cells. The VHDL design of an ATM layer switch meeting these requirements is discussed. The switching requirements of the different layers of the protocol model is presented based on standards documents. In addition, ways of dividing the functionality of the management and signalling planes are described with the goal of optimizing the performance of the ATM switching system

URLhttp://dx.doi.org/10.1109/PACRIM.1995.519419
DOI10.1109/PACRIM.1995.519419

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