An FPGA Design Project: Creating a PowerPC Subsystem Plus User Logic

TitleAn FPGA Design Project: Creating a PowerPC Subsystem Plus User Logic
Publication TypeConference Paper
Year of Publication2007
AuthorsFoist, R., A. Ivanov, and R. Turner
Conference NameMicroelectronic Systems Education, 2007. MSE '07. IEEE International Conference on
Pagination127 -128
Date Publishedjun.
Keywordsdesign database, embedded PowerPC subsystem, embedded processor design, embedded systems, field programmable gate arrays, FPGA design project, hardware-software co-design, hardware-software codesign, logic CAD, processor block, system-on-chip, system-on-chip design, tutorial document, user logic, Xilinx field programmable gate array
Abstract

This paper presents a reference design and tutorial for an embedded PowerPC subsystem with user logic in a Xilinx Field Programmable Gate Array (FPGA). The design and tutorial were created to help graduate students who are doing research in complex electronic applications and want to prototype their designs in an FPGA. Specifically, the design provides a starting point for any application that requires an embedded processor plus user logic that is external to the processor block, but must interface to it. This design project provides a practical introduction to System-on- Chip (SOC) design, embedded processor design, hardware-software co-design, and general FPGA development. The design database and tutorial document can be downloaded from a website at The University of British Columbia (UBC).

URLhttp://dx.doi.org/10.1109/MSE.2007.22
DOI10.1109/MSE.2007.22

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