Time domain multiplexed TAM: implementation and comparison

TitleTime domain multiplexed TAM: implementation and comparison
Publication TypeConference Paper
Year of Publication2003
AuthorsEbadi, Z. S., and A. Ivanov
Conference NameDesign, Automation and Test in Europe Conference and Exhibition, 2003
Pagination732 - 737
Keywordsautomatic test equipment, automatic testing, built-in self test, bus-based TAM, core-based SoC, embedded core testing, integrated circuit testing, network-processing engine SoC, optimal test time, optimisation, P1500 compatible, P1500 wrapper, reconfigurability, scalability, SOC testing, system-on-chip, test access mechanism, time division multiplexing, time domain multiplexed TAM

One of the difficult problems which core-based system-on-chip (SoC) designs face is test access. For testing the cores in a SoC, a special mechanism is required, since they are not directly accessible via chip inputs and outputs. In this paper we introduce a novel Test Access Mechanism (TAM) based on time domain multiplexing (TDM-TAM). This TAM is P1500 compatible and uses a P1500 wrapper The TAM characteristics are its flexibility, scalability, and reconfigurability. The proposed TAM is compared with two other approaches: a serial threading approach analogous to the IEEE] 149.1 standard (Serial TAM) and a packet-switching test network (NIMA). A network-processing engine SoC is used as a platform to compare the different TAMs. Results show that in most cases, TDM is the most effective TAM in both test time and overhead area.


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