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| Title | Non-intrusive testing of high-speed CML circuits |
| Publication Type | Conference Paper |
| Year of Publication | 1998 |
| Authors | Devdas, V., and A. Ivanov |
| Conference Name | Test Symposium, 1998. ATS '98. Proceedings. 7th Asian |
| Pagination | 172 -178 |
| Date Published | dec. |
| Keywords | at-speed tests, bipolar logic circuits, catastrophic open faults, catastrophic short faults, common-mode test, current mode logic circuits, current-mode logic, differential input CML circuits, fault coverage, fault location, functional tests, high-speed CML circuits, high-speed integrated circuits, high-speed interface circuits, Idd test, integrated circuit testing, logic testing, manufacturing defects, nonintrusive testing, PISO, production phase testing, production testing, SONET SIPO, voltage levels |
| Abstract | A new methodology for production phase testing of catastrophic short and open faults in Current Mode Logic (CML) circuits is proposed. The catastrophic faults induced in differential input CML circuits due to manufacturing defects are detected by manipulating the voltage levels of the inputs. The non-intrusive tests include functional (at-speed) tests, Idd test, and a new test called common-mode test (CMT). Two high-speed interface circuits, a 622 Mbps SONET SIPO (Serial-in-Parallel-Out) and a PISO (Parallel-In-Serial-Out) are used as examples to illustrate the effectiveness of the tests. Using all three tests, SPICE simulations show that 88-90% fault coverage of catastrophic faults can be detected |
| URL | http://dx.doi.org/10.1109/ATS.1998.741610 |
| DOI | 10.1109/ATS.1998.741610 |