The University of British Columbia

In recent work, we proposed BackSpace, a new paradigm for using formal analysis, augmented with some on-chip hardware, to support post-silicon debugging. BackSpace allows the chip to run at full speed, but then provides the effect of being able to run backwards from a crash or observed bug, computing a trace of exactly what led up to the problem. In the original paper, we presented the theoretical framework and some preliminary simulation results. This paper recapitulates the basics of the theory and then presents our results moving BackSpace to a more realistic design: an OpenRISC 1200 processor implemented in hardware (FPGA). The result is successful, we can run simple software on the processor, at full speed, but then stop the chip at arbitrary states and back up for hundreds of cycles.