Architecture of cluster-based FPGAs with memory

TitleArchitecture of cluster-based FPGAs with memory
Publication TypeConference Paper
Year of Publication2000
AuthorsClifford, J. P., and S. J. E. Wilton
Conference NameCustom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000
Pagination131 -134
Keywordscellular arrays, cluster-based FPGAs, embedded memory, embedded systems, field programmable gate arrays, logic cluster, memory array, overall speed
Abstract

Embedded memory has become an essential part of FPGAs. In this paper, we investigate how a particular FPGA architecture can be enhanced by including a single memory array in each logic cluster. It is shown that the best overall speed and density results when a cluster contains between 16 and 20 logic elements and one memory array with 512 or 1024 bits. It is also shown that 40% of the logic and memory element inputs should be available outside the cluster

URLhttp://dx.doi.org/10.1109/CICC.2000.852633
DOI10.1109/CICC.2000.852633

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