HIGH Performance Computing Systems and Applications
Volume
657
Pagination
187–205
Abstract
In this paper, we present two mechanisms that reduce indirect mispredictions of two-stage branch predictors: First, to reduce conflict misses in the first stage predictor, a new cache scheme is proposed instead of a branch target buffer (BTB). Second, to reduce mispredictions caused by the second stage predictor, efficient predict and update rules are proposed. We have developed a simulation program by using Shade and Spixtools, provided by SUN Microsystems, on an Ultra SPARC/10 processor. Our results show good improvement with these mechanisms compared to other indirect two-stage predictors.