An efficient instruction cache scheme for object-oriented languages

TitleAn efficient instruction cache scheme for object-oriented languages
Publication TypeConference Paper
Year of Publication2001
AuthorsChu, Y., and M. R. Ito
Conference NamePerformance, Computing, and Communications, 2001. IEEE International Conference on.
Pagination329 -336
Date Publishedapr.
Keywordsbank selection mechanism, Branch Target Buffers, C, C++, cache storage, conflict misses, correction mechanism, efficient instruction cache scheme, instruction cache misses, microprocessors, multi-instruction issue, N-way banks, object-oriented application programs, object-oriented languages, performance evaluation, procedure call/returns, Shade, simulation program, skewed-associative caches, Spixtools, SUN Microsystems, system performance, ultra SPARC/10 processor, XOR mapping functions

We present an efficient cache scheme, which can considerably reduce instruction cache misses caused by procedure call/returns. This scheme employs N-way banks and XOR mapping functions. The main function of this scheme is to place a group of instructions separated by a call instruction into a bank according to the initial and final bank selection mechanisms. After the initial bank selection mechanism selects a bank on an instruction cache miss, the final bank selection mechanism will determine the final bank for updating a cache line as a correction mechanism. These two mechanisms can guarantee that recent groups of instructions exist in each bank safely. We have developed a simulation program by using Shade and Spixtools, provided by SUN Microsystems, on an ultra SPARC/10 processor. Our experimental results show that these schemes reduce conflict misses more effectively than skewed-associative caches in both C (up to 9.29% improvement) and C++ (up to 30.71% improvement) programs on L1 caches. In addition, they also allow for a significant miss reduction on Branch Target Buffers (BTB)


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