Title | The 2-way thrashing-avoidance cache (TAC): an efficient instruction cache scheme for object-oriented languages |
Publication Type | Conference Paper |
Year of Publication | 2000 |
Authors | Chu, Y., and M. R. Ito |
Conference Name | Computer Design, 2000. Proceedings. 2000 International Conference on |
Pagination | 93 -98 |
Keywords | 2-way banks, 2-way thrashing-avoidance cache, bank selection logic, bank-originated pseudo-LRU replacement policies, C++ programs, cache storage, call instruction, conflict misses, instruction cache scheme, object-oriented languages, object-oriented programming, Shade, simulation program, Spixtools, TACSim, ultra SPARC/10 processor, XOR mapping functions |
Abstract | This paper presents a new instruction cache scheme: the TAC (Thrashing-Avoidance Cache). A 2-way TAC scheme employs 2-way banks and XOR mapping functions. The main function of the TAC is to place a group of instructions separated by a call instruction into a bank according to the Bank Selection Logic (BSL) and Bank-originated Pseudo-LRU replacement policies (BoPLRU). After the BSL initially selects a bank on an instruction cache miss, the BoPLRU will determine the final bank for updating a cache line as a correction mechanism. These two mechanisms can guarantee that recent groups of instructions exist in each bank safely. We have developed a simulation program, TACSim, by using Shade and Spixtools, provided by SUN Microsystems, on an ultra SPARC/10 processor. Our experimental results show that 2-way TAC schemes reduce conflict misses more effectively than 2-way skewed-associative caches in both C (17% improvement) and C++ (30% improvement) programs on L1 caches |
URL | http://dx.doi.org/10.1109/ICCD.2000.878273 |
DOI | 10.1109/ICCD.2000.878273 |