A comparison of CMOS circuit techniques: differential cascode voltage switch logic versus conventional logic

TitleA comparison of CMOS circuit techniques: differential cascode voltage switch logic versus conventional logic
Publication TypeJournal Article
Year of Publication1987
AuthorsCHU, K. M., and D. L. Pulfrey
JournalSolid-State Circuits, IEEE Journal of
Volume22
Pagination528 - 532
Date Publishedaug.
ISSN0018-9200
KeywordsCircuit analysis computing, CMOS integrated circuits, Integrated logic circuits
Abstract

Differential cascode voltage switch (DCVS) logic is a CMOS circuit technique that has potential advantages over conventional NAND/NOR logic in terms of circuit delay, layout density, power dissipation, and logic flexibility. A detailed comparison of DCVS logic and conventional logic is carried out by simulation, using SPICE, of the performance of full adders designed using the different circuit techniques. The parameters compared are: input gate capacitance, number of transistors required, propagation delay time, and average power dissipation. In the static case, DCVS appears to be superior to full CMOS in regards to input capacitance and device count but inferior in regards to power dissipation. The speeds of the two technologies are similar. In the dynamic case, DCVS can be faster than more conventional CMOS dynamic logic, but only at the expense of increased device count and power dissipation.

URLhttp://dx.doi.org/10.1109/JSSC.1987.1052767
DOI10.1109/JSSC.1987.1052767

a place of mind, The University of British Columbia

Electrical and Computer Engineering
2332 Main Mall
Vancouver, BC Canada V6T 1Z4
Tel +1.604.822.2872
Fax +1.604.822.5949
Email:

Emergency Procedures | Accessibility | Contact UBC | © Copyright 2020 The University of British Columbia