Dynamic voltage scaling for commercial FPGAs

TitleDynamic voltage scaling for commercial FPGAs
Publication TypeConference Paper
Year of Publication2005
AuthorsChow, C. T., L. S. M. Tsui, P. H. W. Leong, W. Luk, and S. J. E. Wilton
Conference NameField-Programmable Technology, 2005. Proceedings. 2005 IEEE International Conference on
Pagination173 -180
Date Publisheddec.
Keywordsclosed loop control scheme, closed loop systems, delay circuits, dynamic voltage scaling, field programmable gate array, field programmable gate arrays, inverter chain speed, logic delay measurement circuit, logic design

A methodology for supporting dynamic voltage scaling (DVS) on commercial FPGAs is described. A logic delay measurement circuit (LDMC) is used to determine the speed of an inverter chain for various operating conditions at run time. A desired LDMC value, intended to match the critical path of the operating circuit plus a safety margin, is then chosen; a closed loop control scheme is used to maintain the desired LDMC value as chip temperature changes, by automatically adjusting the voltage applied to the FPGA. We describe experiments using this technique on various circuits at different clock frequencies and temperatures to demonstrate its utility and robustness. Power savings between 4% and 54% for the VINT supply are observed


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