A low power based system partitioning and binding technique for multi-chip module architectures

TitleA low power based system partitioning and binding technique for multi-chip module architectures
Publication TypeConference Paper
Year of Publication1997
AuthorsCherabuddi, R. V., M. A. Bayoumi, and H. Krishnamurthy
Conference NameVLSI, 1997. Proceedings. 7th Great Lakes Symposium on
Pagination156 -162
Date Publishedmar.
Keywordsbenchmark designs, binding technique, circuit layout CAD, functional units, high level synthesis, high-level synthesis framework, integrated circuit interconnections, inter-chip buses, logic partitioning, MCM, multi-chip module architectures, multichip modules, stochastic evolution based technique, stochastic processes, switching activity, system partitioning
Abstract

In this paper, we present a low power targeted high-level synthesis framework for the synthesis of Multi-Chip Modules (MCM). This new framework is based on minimizing the switching activity on the functional units as well as the inter-chip buses. The main focus of the developed method is minimizing the power during partitioning and binding phases of high-level synthesis. A Stochastic Evolution based technique has been used for system partitioning. Experimental results were highly encouraging with power reduction of up to 60% on certain benchmark designs

URLhttp://dx.doi.org/10.1109/GLSV.1997.580530
DOI10.1109/GLSV.1997.580530

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