An FPGA receiver for CPSK spread spectrum signaling

TitleAn FPGA receiver for CPSK spread spectrum signaling
Publication TypeJournal Article
Year of Publication1999
AuthorsChan, S. K. S., and V. C. M. Leung
JournalConsumer Electronics, IEEE Transactions on
Volume45
Pagination181 -191
Date Publishedfeb.
ISSN0098-3063
Keywordscarrier-phase synchronization, code acquisition, code-phase-shift keying, Costas loop, CPSK baseband decoder, CPSK spread spectrum signaling, design, double threshold detection scheme, field programmable gate array, field programmable gate arrays, FPGA receiver, IF demodulator, implementation, indoor radio, M-ary direct sequence spread spectrum receiver, modified double-dwell serial search scheme, modulation coding, phase shift keying, pseudonoise code sequence, pseudonoise codes, radio receivers, receiver performance, search problems, spread spectrum communication, synchronisation, telecommunication equipment testing, telecommunication signalling, testing, tracking, wireless home networking
Abstract

In this paper, we present the design, implementation and testing of an M-ary direct sequence spread spectrum receiver suitable for wireless home networking applications. The receiver employs a novel code-phase-shift keying (CPSK) signaling scheme, in which each of the M signaling waveforms is derived from a different phase shift of a single pseudonoise code sequence. The receiver consists of an IF demodulator and a CPSK baseband decoder, implemented using discrete components and an FPGA (field programmable gate array) chip, respectively. A modified double-dwell serial search scheme is used for code acquisition and tracking, and the carrier-phase synchronization is solved by a Costas loop in the IF demodulator and a double threshold detection scheme in the CPSK decoder. Measurements of receiver performance are presented and compared with theoretical calculations

URLhttp://dx.doi.org/10.1109/30.754435
DOI10.1109/30.754435

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