A variable rate constraint length K=5 Viterbi decoder for 12 Mb/s

TitleA variable rate constraint length K=5 Viterbi decoder for 12 Mb/s
Publication TypeConference Paper
Year of Publication1993
AuthorsBonek, P., A. Ivanov, and S. Kallel
Conference NameElectrical and Computer Engineering, 1993. Canadian Conference on
Pagination582 -585 vol.1
Date Publishedsep.
Keywords12 Mbit/s, application specific integrated circuits, architecture, area efficient testing schemes, bit-serial node-parallel, butterflies, CMOS integrated circuits, codecs, convolutional codes, custom layout, decoder chip, decoding, digital signal processing chips, interconnect area, maximum likelihood estimation, memory architecture, memory elements, modulo normalization, parallel architectures, path memory, Si, Si area, single stuck-at-fault coverage, surviving path metrics, variable rate constraint length K=5 Viterbi decoder, VLSI

Describes a fully testable variable rate Viterbi decoder chip capable of decoding convolutional codes ranging from rate 7/8 to 1/4 derived from the same 1/2 rate code. The architecture of the Viterbi decoder is bit-serial node-parallel to save interconnect area but still achieve high speed decoding. Modulo normalization of the surviving path metrics, arranging the memory elements of the path memory as sets of butterflies, and custom layout are the key for reducing the Si area. Newly developed area efficient testing schemes achieve 99.9% single stuck-at-fault coverage, while requiring lt;5% hardware overhead


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