A DSP-based implementation of a turbo-decoder

TitleA DSP-based implementation of a turbo-decoder
Publication TypeConference Paper
Year of Publication1998
AuthorsBlazek, Z., and V. K. Bhargava
Conference NameGlobal Telecommunications Conference, 1998. GLOBECOM 98. The Bridge to Global Integration. IEEE
Pagination2751 -2755 vol.5
Keywords10 kbit/s, 192 bit, AWGN channels, block interleaver, code constraint length, constituent codes, convolutional code, data rate, digital signal processing chips, DSP-based implementation, interleaved codes, iterations, Iterative Decoding, NASA standard, Rayleigh channels, Rayleigh fading channels, single DSP chip, SOVA-based turbo-decoder, turbo codes, turbo-decoder, Viterbi decoder, Viterbi decoding

This paper focuses on a DSP based implementation of a decoder for a simple turbo-code, consisting of two constituent codes of constraint length three and a 192 bit block interleaver. With three full iterations of the SOVA-based turbo-decoder executing on a single DSP chip, a data rate of approximately 10 kbps can be achieved. This implementation is then compared against a Viterbi decoder for the ldquo;NASA standard rdquo; constraint length seven convolutional code


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