On the testability of CMOS feedback amplifiers

TitleOn the testability of CMOS feedback amplifiers
Publication TypeConference Paper
Year of Publication1994
AuthorsBishop, A. J., and A. Ivanov
Conference NameDefect and Fault Tolerance in VLSI Systems, 1994. Proceedings., The IEEE International Workshop on
Pagination65 -73
Date Publishedoct.
Keywordscatastrophic faults, closed loop configurations, CMOS feedback amplifiers, comparator, differentiator, fault condition, faulty response, integrated circuit testing, integrator, inverting amplifier, Monte Carlo fault simulations, network configurations, open faults, operational amplifier, parameter variation fault models, short faults, sine wave, stuck-at faults, test stimulus, testability, wafer probe
Abstract

This paper examines the testability of a CMOS operational amplifier (op-amp) in four different feedback configurations. Feedback is often considered to complicate the testing problem. Here, we illustrate that it is possible to test the op-amp for catastrophic faults at wafer probe without having to remove feedback structures. Catastrophic, as well as parameter variation fault models, are used to simulate the faulty response of the opamp circuits. Our method relies on repeated Monte Carlo fault simulations to examine differences in a circuit's response for each possible fault condition. A sine wave is used for the test stimulus in each case. Four closed loop configurations are considered for the study: integrator, differentiator, inverting amplifier, and comparator. We tally the percentage of stuck-at, short, and open faults that are detectable with the feedback applied to demonstrate that the four feedback network configurations have little effect on the catastrophic fault coverage, as compared with similar tests performed for an open-loop configuration

URLhttp://dx.doi.org/10.1109/DFTVS.1994.630015
DOI10.1109/DFTVS.1994.630015

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