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| Title | Digital control with improved performance for boost power factor correction circuits |
| Publication Type | Conference Paper |
| Year of Publication | 2001 |
| Authors | Bibian, S., and H. Jin |
| Conference Name | Applied Power Electronics Conference and Exposition, 2001. APEC 2001. 16th Annual IEEE |
| Pagination | 137 -143 vol.1 |
| Keywords | boost power factor correction circuits, computational delays, control system synthesis, DC-DC power convertors, dead-beat control, digital control, digital controller design, large control periods, PFC pre-regulator, power factor correction, predictive control, system specifications, very low control rate |
| Abstract | In this paper, an approach for the design of a digital controller for a PFC pre-regulator is proposed. The controller is modified to account for large control periods and computational delays, and can therefore be implemented on processors with few available computational resources. Results show that, even with a very low control rate, system specifications can be met using the proposed technique |
| URL | http://dx.doi.org/10.1109/APEC.2001.911639 |
| DOI | 10.1109/APEC.2001.911639 |