Performance evaluation of a FFT using adpative clocking

TitlePerformance evaluation of a FFT using adpative clocking
Publication TypeConference Paper
Year of Publication2008
AuthorsBagnordi, H., and M. Ito
Conference NameSOC Conference, 2008 IEEE International
Pagination135 -138
Date Publishedsep.
Keywordsadaptive clocking, clocks, dynamic power consumption, fast Fourier transform, fast Fourier transforms, FFT, field programmable gate arrays, FPGA, performance evaluation, processing speed
Abstract

This paper presents an experimental evaluation on the feasibility of using an adaptive clock to enhance the performance of a Fast Fourier Transform (FFT). The FFT is implemented on an FPGA and results are simulated using commercial EDA tools. Dynamic power consumption and processing speed are compared to a standard FFT implementation using a fixed clock. Results show that using a dynamically variable frequency clock offers a potential speed improvement while maintaining energy efficiency.

URLhttp://dx.doi.org/10.1109/SOCC.2008.4641496
DOI10.1109/SOCC.2008.4641496

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