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| Title | Performance evaluation of a FFT using adpative clocking |
| Publication Type | Conference Paper |
| Year of Publication | 2008 |
| Authors | Bagnordi, H., and M. Ito |
| Conference Name | SOC Conference, 2008 IEEE International |
| Pagination | 135 -138 |
| Date Published | sep. |
| Keywords | adaptive clocking, clocks, dynamic power consumption, fast Fourier transform, fast Fourier transforms, FFT, field programmable gate arrays, FPGA, performance evaluation, processing speed |
| Abstract | This paper presents an experimental evaluation on the feasibility of using an adaptive clock to enhance the performance of a Fast Fourier Transform (FFT). The FFT is implemented on an FPGA and results are simulated using commercial EDA tools. Dynamic power consumption and processing speed are compared to a standard FFT implementation using a fixed clock. Results show that using a dynamically variable frequency clock offers a potential speed improvement while maintaining energy efficiency. |
| URL | http://dx.doi.org/10.1109/SOCC.2008.4641496 |
| DOI | 10.1109/SOCC.2008.4641496 |