Power, Delay and Yield Analysis of BIST/BISR PLAs Using Column Redundancy

TitlePower, Delay and Yield Analysis of BIST/BISR PLAs Using Column Redundancy
Publication TypeConference Paper
Year of Publication2007
AuthorsAlsaiari, U., and R. Saleh
Conference NameQuality Electronic Design, 2007. ISQED '07. 8th International Symposium on
Pagination703 -710
Date Publishedmar.
KeywordsBIST/BISR PLA, block duplication strategy, built-in self test, built-in-self-repair, built-in-self-test, column redundancy, delay analysis, integrated circuit yield, power analysis, programmable logic arrays, redundancy, yield analysis

As the number of transistors on a chip begins to exceed 1 billion, it is mandatory to use a portion of the transistors for the purposes of built-in-self-test (BIST) and built-in-self-repair (BISR) as part of the supporting circuitry. However, this requires the use of structured logic, such as programmable logic arrays (PLAs) or structured ASIC. In this paper, we select the fastest and lowest energy PLA design to date and combine it with a block duplication strategy to construct a BIST/BISR PLA in order to establish a reference design. Then, we introduce a PLA redundancy in the form of spare columns and carry out a yield analysis. The results of the yield analysis suggest that using duplication for BIST/BISR is better suited for small PLAs while using spares is more suitable for larger PLAs. The spares needed are determined by several factors including target yield, area, power and delay


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